clock division in two in verilog -

i trying divide input clock 2 i.e output clock should half frequency of input clock.

module clk_div(in_clk, out_clk, rst);   input  in_clk;   input  rst;   output out_clk;   reg    out_clk;  @(posedge in_clk) begin   if (!rst) begin     out_clk <= 1'b0;   end   else      out_clk <= ~out_clk; end endmodule 

the testbench is

module dd;   // inputs   reg clk_in;   reg reset;    // outputs   wire clk_out;    // instantiate unit under test (uut)   clk_div uut (     .clk_in(clk_in),      .reset(reset),      .clk_out(clk_out)   );    #10 clk_in =~clk_in ;    initial begin     // initialize inputs     clk_in = 0;     reset  = 0;     #100;     reset  = 1;   end    endmodule 

the output waveform shows input clock being generated. no matter try output clock waveform not come. code correct clock division two?

you need change port names in instance. change instance to:

clk_div uut (     .in_clk(clk_in),      .rst(reset),      .out_clk(clk_out) ); 

i divide-by-2 fix.

your code had compile errors on 2 simulators me. did compile you?